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[SCM] VHDL

Description: 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化 -Note 1: contains a comprehensive statement can not, please amend Note 2: Some PLD only permit I/O port of external tri-state, does not support internal tri-state, the use of when we should pay attention Note 3: the design of RAM
Platform: | Size: 44032 | Author: 朱明 | Hits:

[VHDL-FPGA-Verilog] VHDL________

Description: VHDL programming samples WORD DOC FILE
Platform: | Size: 4096 | Author: kofway | Hits:

[VHDL-FPGA-Verilog] fpga_sample_program

Description: 学习vhdl硬件描述语言的一些例子的原代码，比较全面，相信对初学者很有帮助-VHDL hardware description language to learn some examples of the original code, a more comprehensive, I believe very helpful for beginners
Platform: | Size: 254976 | Author: 马斌 | Hits:

[VHDL-FPGA-Verilog] ramlib_06

Description: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。-This is a FIFO of the VHDL program. . . Please download the U.S. share.
Platform: | Size: 577536 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用-Synchronous Dynamic RAM control circuit VHDL source code, in the SOC development can be applied directly
Platform: | Size: 90112 | Author: 26 | Hits:

[VHDL-FPGA-Verilog] memio

Description: 最新VHDL 模块，实现对SRAM的控制，能直接用在ALTEAR XILLIX 等 FPGA上，-Latest VHDL modules to realize the control of SRAM can be directly used for ALTEAR XILLIX such as FPGA, the
Platform: | Size: 7168 | Author: 骑士 | Hits:

[Other] a2d2

Description: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
Platform: | Size: 180224 | Author: | Hits:

[VHDL-FPGA-Verilog] mif

Description: 编制FPGA中RAM所需要的MIF文件 编制FPGA中RAM所需要的MIF文件-FPGA in the preparation of RAM required for the preparation of MIF files in the RAM of the FPGA needs MIF file
Platform: | Size: 1936384 | Author: 史东升 | Hits:

[VHDL-FPGA-Verilog] 32×4bitRAM

Description: 32×4bit 的RAM设计。VHD语言。能在ISE上仿真。-32 × 4bit the RAM design. VHD language. The simulation in ISE.
Platform: | Size: 3072 | Author: 张军 | Hits:

[VHDL-FPGA-Verilog] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家-VHDL the ram and fifo model code contains a large number of manufacturers
Platform: | Size: 1678336 | Author: SL | Hits:

[VHDL-FPGA-Verilog] dualporttst-1_0

Description: xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
Platform: | Size: 195584 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] doubleportram

Description: 高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
Platform: | Size: 303104 | Author: liujingxing | Hits:

[Embeded-SCM Develop] quartus

Description:
Platform: | Size: 10531840 | Author: liuhongjie | Hits:

[VHDL-FPGA-Verilog] DPRAM

Description: 利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
Platform: | Size: 1024 | Author: 孙敬辉 | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[VHDL-FPGA-Verilog] ram_old

Description: 用来测试cpu的ram代码 其中包括几十条指令 cpu的vhdl也在本站有下-Cpu the ram used to test the code, including dozens of VHDL cpu instructions also have a website under the
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[VHDL-FPGA-Verilog] RAMtestbench

Description: 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
Platform: | Size: 1024 | Author: 赵国栋 | Hits:

[Other] rom

Description: 根据实验要求，对rom和ram进行验证，实现各项功能。-According to the experimental requirements of rom and ram for authentication, the realization of various functions.
Platform: | Size: 70656 | Author: cgrcgh | Hits:

[VHDL-FPGA-Verilog] wave_produce_VHDL

Description: --文件名：mine4.vhd。 --功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节量阶为1/51V）。 --其中方波的幅度还可通过u0、d0调节输出数据的归一化幅值（AMP0）进行进一步 --细调（调节量阶为1/（51*255）V）。方波A的占空比通过zu、zp按键调节（调节 --量阶1/64*T）。系统采用内部存储器——RAM实现任意输入波形的存储，程序只支 --持键盘式波形特征参数置入存储，posting 为进入任意波置入(set)、清除（clr）状态 --控制信号，SSS控制存储波形的输出。P180为预留端口， -err
Platform: | Size: 10240 | Author: huangsong | Hits:
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